modification logiciel pilotage 4 ports = 32 entrees
This commit is contained in:
parent
171b41e78f
commit
ca78f11b58
@ -1,18 +1,55 @@
|
||||
|
||||
|
||||
/* travail du 20/09/2019 modification du cablage pour essai gestion par port
|
||||
/* travail du 11/10/2019 modification pour 32 entrées
|
||||
|
||||
|
||||
| port A | Broche | note | MIDI hex |
|
||||
| -------- | -------- | -------- | -------- |
|
||||
| A0 | 22 | C2 | 24 |
|
||||
| A1 | 23 | D2 | 26 |
|
||||
| A2 | 24 | E2 | 28 |
|
||||
| A3 | 25 | F2 | 29 |
|
||||
| A4 | 26 | G2 | 2B |
|
||||
| A5 | 27 | A2 | 2D |
|
||||
| A6 | 28 | B2 | 2F |
|
||||
| A7 | 29 | C3 | 30 |
|
||||
| A1 | 23 | C2# | 25 |
|
||||
| A2 | 24 | D2 | 26 |
|
||||
| A3 | 25 | D2# | 27 |
|
||||
| A4 | 26 | E2 | 28 |
|
||||
| A5 | 27 | F2 | 29 |
|
||||
| A6 | 28 | F2# | 2A |
|
||||
| A7 | 29 | G2 | 2B |
|
||||
|
||||
|
||||
| port B | Broche | note | MIDI hex |
|
||||
| -------- | -------- | -------- | -------- |
|
||||
| B0 | 53 | G2# | 2C |
|
||||
| B1 | 52 | A2 | 2D |
|
||||
| B2 | 51 | A2# | 2E |
|
||||
| B3 | 50 | B2 | 2F |
|
||||
| B4 | 10 | C3 | 30 |
|
||||
| B5 | 11 | C3# | 31 |
|
||||
| B6 | 12 | D3 | 32 |
|
||||
| B7 | 13 | D3# | 33 |
|
||||
|
||||
|
||||
| port C | Broche | note | MIDI hex |
|
||||
| -------- | -------- | -------- | -------- |
|
||||
| C0 | 37 | E3 | 34 |
|
||||
| C1 | 36 | F3 | 35 |
|
||||
| C2 | 35 | F3# | 36 |
|
||||
| C3 | 34 | G3 | 37 |
|
||||
| C4 | 33 | G3# | 38 |
|
||||
| C5 | 32 | A3 | 39 |
|
||||
| C6 | 31 | A3# | 3A |
|
||||
| C7 | 30 | B3 | 3B |
|
||||
|
||||
|
||||
| port L | Broche | note | MIDI hex |
|
||||
| -------- | -------- | -------- | -------- |
|
||||
| L0 | 49 | C4 | 3C |
|
||||
| L1 | 48 | C4# | 3D |
|
||||
| L2 | 47 | D4 | 3E |
|
||||
| L3 | 46 | D4# | 3F |
|
||||
| L4 | 45 | E4 | 40 |
|
||||
| L5 | 44 | F4 | 41 |
|
||||
| L6 | 43 | F4# | 42 |
|
||||
| L7 | 42 | G4 | 43 |
|
||||
|
||||
|
||||
|
||||
*/
|
||||
@ -29,31 +66,96 @@
|
||||
const int Masque128 = B10000000 ;
|
||||
|
||||
|
||||
int RegistreA = 0xFF ;
|
||||
int RegistreA = 0xFF ; /* initialisation registre A */
|
||||
|
||||
|
||||
int RegistreB = 0xFF ; /* initialisation registre B */
|
||||
int RegistreC = 0xFF ; /* initialisation registre C */
|
||||
int RegistreL = 0xFF ; /* initialisation registre L */
|
||||
|
||||
|
||||
|
||||
|
||||
int EPA0 = B00000001 ; /* variable pour l'utilisation du port A */
|
||||
int EPA1 = B00000010 ; //
|
||||
int EPA2 = B00000100 ; //
|
||||
int EPA3 = B00001000 ; //
|
||||
int EPA4 = B00010000 ; //
|
||||
int EPA5 = B00100000 ; //
|
||||
int EPA6 = B01000000 ; //
|
||||
int EPA7 = B10000000 ; //
|
||||
|
||||
int DePA0 = 1 ; //
|
||||
int DePA1 = 2 ; //
|
||||
int DePA2 = 4 ; //
|
||||
int DePA3 = 8 ; //
|
||||
int DePA4 = 16 ; //
|
||||
int DePA5 = 32 ; //
|
||||
int DePA6 = 64 ; //
|
||||
int DePA7 = 128 ; //
|
||||
|
||||
int EPB0 = B00000001 ; /* variable pour l'utilisation du port B */
|
||||
int EPB1 = B00000010 ; //
|
||||
int EPB2 = B00000100 ; //
|
||||
int EPB3 = B00001000 ; //
|
||||
int EPB4 = B00010000 ; //
|
||||
int EPB5 = B00100000 ; //
|
||||
int EPB6 = B01000000 ; //
|
||||
int EPB7 = B10000000 ; //
|
||||
|
||||
int DePB0 = 1 ; //
|
||||
int DePB1 = 2 ; //
|
||||
int DePB2 = 4 ; //
|
||||
int DePB3 = 8 ; //
|
||||
int DePB4 = 16 ; //
|
||||
int DePB5 = 32 ; //
|
||||
int DePB6 = 64 ; //
|
||||
int DePB7 = 128 ; //
|
||||
|
||||
|
||||
|
||||
int EPC0 = B00000001 ; /* variable pour l'utilisation du port C */
|
||||
int EPC1 = B00000010 ; //
|
||||
int EPC2 = B00000100 ; //
|
||||
int EPC3 = B00001000 ; //
|
||||
int EPC4 = B00010000 ; //
|
||||
int EPC5 = B00100000 ; //
|
||||
int EPC6 = B01000000 ; //
|
||||
int EPC7 = B10000000 ; //
|
||||
|
||||
int DePC0 = 1 ; //
|
||||
int DePC1 = 2 ; //
|
||||
int DePC2 = 4 ; //
|
||||
int DePC3 = 8 ; //
|
||||
int DePC4 = 16 ; //
|
||||
int DePC5 = 32 ; //
|
||||
int DePC6 = 64 ; //
|
||||
int DePC7 = 128 ; //
|
||||
|
||||
|
||||
int EPL0 = B00000001 ; /* variable pour l'utilisation du port L */
|
||||
int EPL1 = B00000010 ; //
|
||||
int EPL2 = B00000100 ; //
|
||||
int EPL3 = B00001000 ; //
|
||||
int EPL4 = B00010000 ; //
|
||||
int EPL5 = B00100000 ; //
|
||||
int EPL6 = B01000000 ; //
|
||||
int EPL7 = B10000000 ; //
|
||||
|
||||
int DePL0 = 1 ; //
|
||||
int DePL1 = 2 ; //
|
||||
int DePL2 = 4 ; //
|
||||
int DePL3 = 8 ; //
|
||||
int DePL4 = 16 ; //
|
||||
int DePL5 = 32 ; //
|
||||
int DePL6 = 64 ; //
|
||||
int DePL7 = 128 ; //
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int EPA0 = B00000001 ;
|
||||
int EPA1 = B00000010 ;
|
||||
int EPA2 = B00000100 ;
|
||||
int EPA3 = B00001000 ;
|
||||
int EPA4 = B00010000 ;
|
||||
int EPA5 = B00100000 ;
|
||||
int EPA6 = B01000000 ;
|
||||
int EPA7 = B10000000 ;
|
||||
|
||||
int DePA0 = 1 ;
|
||||
int DePA1 = 2 ;
|
||||
int DePA2 = 4 ;
|
||||
int DePA3 = 8 ;
|
||||
int DePA4 = 16 ;
|
||||
int DePA5 = 32 ;
|
||||
int DePA6 = 64 ;
|
||||
int DePA7 = 128 ;
|
||||
|
||||
|
||||
|
||||
|
||||
@ -61,7 +163,7 @@ int DePA7 = 128 ;
|
||||
|
||||
void setup()
|
||||
{
|
||||
pinMode(22,INPUT);
|
||||
pinMode(22,INPUT); /* port A */
|
||||
pinMode(23,INPUT);
|
||||
pinMode(24,INPUT);
|
||||
pinMode(25,INPUT);
|
||||
@ -70,8 +172,32 @@ void setup()
|
||||
pinMode(28,INPUT);
|
||||
pinMode(29,INPUT);
|
||||
|
||||
pinMode(53,INPUT); /* port B */
|
||||
pinMode(52,INPUT);
|
||||
pinMode(51,INPUT);
|
||||
pinMode(50,INPUT);
|
||||
pinMode(10,INPUT);
|
||||
pinMode(11,INPUT);
|
||||
pinMode(12,INPUT);
|
||||
pinMode(13,INPUT);
|
||||
|
||||
/* DDRA = B11111111 ; /* initialisation du port A en entré sur toutes les broches */
|
||||
pinMode(37,INPUT); /* port C */
|
||||
pinMode(36,INPUT);
|
||||
pinMode(35,INPUT);
|
||||
pinMode(34,INPUT);
|
||||
pinMode(33,INPUT);
|
||||
pinMode(32,INPUT);
|
||||
pinMode(31,INPUT);
|
||||
pinMode(30,INPUT);
|
||||
|
||||
pinMode(49,INPUT); /* port L */
|
||||
pinMode(48,INPUT);
|
||||
pinMode(47,INPUT);
|
||||
pinMode(46,INPUT);
|
||||
pinMode(45,INPUT);
|
||||
pinMode(44,INPUT);
|
||||
pinMode(43,INPUT);
|
||||
pinMode(42,INPUT);
|
||||
|
||||
|
||||
|
||||
@ -79,19 +205,23 @@ void setup()
|
||||
|
||||
|
||||
|
||||
|
||||
/* DDRA = B11111111 ; /* initialisation du port A en entré sur toutes les broches */ /* NE FONCTIONNE PAS ! */
|
||||
/* DDRB = B11111111 ; /* initialisation du port B en entré sur toutes les broches */
|
||||
/* DDRC = B11111111 ; /* initialisation du port C en entré sur toutes les broches */
|
||||
/* DDRL = B11111111 ; /* initialisation du port L en entré sur toutes les broches */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Serial.begin(31250); /* initialisation d'un port serie au debit MIDI */
|
||||
|
||||
for (int i=0x24 ; i<= 0x43 ; i++ )
|
||||
{
|
||||
noteOn( 0x80, i , 0x00 ) ;
|
||||
|
||||
|
||||
noteOn( 0x80, 0x24 , 0x00 ) ;
|
||||
noteOn( 0x80, 0x26 , 0x00 ) ;
|
||||
noteOn( 0x80, 0x28 , 0x00 ) ;
|
||||
noteOn( 0x80, 0x29 , 0x00 ) ;
|
||||
noteOn( 0x80, 0x2B , 0x00 ) ;
|
||||
noteOn( 0x80, 0x2D , 0x00 ) ;
|
||||
noteOn( 0x80, 0x2F , 0x00 ) ;
|
||||
noteOn( 0x80, 0x30 , 0x00 ) ;
|
||||
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
@ -116,8 +246,12 @@ void loop()
|
||||
|
||||
RegistreA = PINA ; /* lecture du port A */
|
||||
|
||||
RegistreB = PINB ; /* lecture du port B */
|
||||
RegistreC = PINC ; /* lecture du port C */
|
||||
RegistreL = PINL ; /* lecture du port L */
|
||||
|
||||
EPA0 = RegistreA & Masque1 ;
|
||||
|
||||
EPA0 = RegistreA & Masque1 ; /* gestion du port A */
|
||||
EPA1 = RegistreA & Masque2 ;
|
||||
EPA2 = RegistreA & Masque4 ;
|
||||
EPA3 = RegistreA & Masque8 ;
|
||||
@ -126,40 +260,141 @@ void loop()
|
||||
EPA6 = RegistreA & Masque64 ;
|
||||
EPA7 = RegistreA & Masque128 ;
|
||||
|
||||
if ( ( EPA0 == 0 ) && ( DePA0 == 1 ) ) { noteOn(0x90, 0x24 , 0x70 ) ; }
|
||||
if ( ( EPA0 == 1 ) && ( DePA0 == 0 ) ) { noteOn(0x80, 0x24 , 0x00 ) ;}
|
||||
if ( ( EPA0 == 0 ) && ( DePA0 == 1 ) ) { noteOn(0x90, 0x24 , 0x70 ) ; }
|
||||
if ( ( EPA0 == 1 ) && ( DePA0 == 0 ) ) { noteOn(0x80, 0x24 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA1 == 0 ) && ( DePA1 == Masque2 ) ) noteOn(0x90, 0x25 , 0x70 ) ;
|
||||
if ( ( EPA1 == Masque2 ) && ( DePA1 == 0 ) ) noteOn(0x80, 0x25 , 0x00 ) ;
|
||||
|
||||
if ( ( EPA2 == 0 ) && ( DePA2 == Masque4 ) ) { noteOn(0x90, 0x26 , 0x70 ) ;}
|
||||
if ( ( EPA2 == Masque4 ) && ( DePA2 == 0 ) ) { noteOn(0x80, 0x26 , 0x00 ) ; }
|
||||
|
||||
if ( ( EPA3 == 0 ) && ( DePA3 == Masque8 ) ) { noteOn(0x90, 0x27 , 0x70 ) ;}
|
||||
if ( ( EPA3 == Masque8 ) && ( DePA3 == 0 ) ) {noteOn(0x80, 0x27 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA4 == 0 ) && ( DePA4 == Masque16 ) ) { noteOn(0x90, 0x28 , 0x70 ) ;}
|
||||
if ( ( EPA4 == Masque16 ) && ( DePA4 == 0 ) ) { noteOn(0x80, 0x28 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA5 == 0 ) && ( DePA5 == Masque32 ) ) { noteOn(0x90, 0x29 , 0x70 ) ;}
|
||||
if ( ( EPA5 == Masque32 ) && ( DePA5 == 0 ) ) { noteOn(0x80, 0x29 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA6 == 0 ) && ( DePA6 == Masque64 ) ) { noteOn(0x90, 0x2A , 0x70 ) ;}
|
||||
if ( ( EPA6 == Masque64 ) && ( DePA6 == 0 ) ) { noteOn(0x80, 0x2A , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA7 == 0 ) && ( DePA7 == Masque128 ) ) { noteOn(0x90, 0x2B , 0x70 ) ;}
|
||||
if ( ( EPA7 == Masque128 ) && ( DePA7 == 0 ) ) { noteOn(0x80, 0x2B , 0x00 ) ;} /* fin de gestion du port A */
|
||||
|
||||
|
||||
EPB0 = RegistreB & Masque1 ; /* gestion du port B */
|
||||
EPB1 = RegistreB & Masque2 ;
|
||||
EPB2 = RegistreB & Masque4 ;
|
||||
EPB3 = RegistreB & Masque8 ;
|
||||
EPB4 = RegistreB & Masque16 ;
|
||||
EPB5 = RegistreB & Masque32 ;
|
||||
EPB6 = RegistreB & Masque64 ;
|
||||
EPB7 = RegistreB & Masque128 ;
|
||||
|
||||
if ( ( EPB0 == 0 ) && ( DePB0 == 1 ) ) { noteOn(0x90, 0x2C , 0x70 ) ; } /* gestion du port B */
|
||||
if ( ( EPB0 == 1 ) && ( DePB0 == 0 ) ) { noteOn(0x80, 0x2C , 0x00 ) ;}
|
||||
|
||||
if ( ( EPB1 == 0 ) && ( DePB1 == Masque2 ) ) noteOn(0x90, 0x2D , 0x70 ) ;
|
||||
if ( ( EPB1 == Masque2 ) && ( DePB1 == 0 ) ) noteOn(0x80, 0x2D , 0x00 ) ;
|
||||
|
||||
if ( ( EPB2 == 0 ) && ( DePB2 == Masque4 ) ) { noteOn(0x90, 0x2E , 0x70 ) ;}
|
||||
if ( ( EPB2 == Masque4 ) && ( DePB2 == 0 ) ) { noteOn(0x80, 0x2E , 0x00 ) ; }
|
||||
|
||||
if ( ( EPB3 == 0 ) && ( DePB3 == Masque8 ) ) { noteOn(0x90, 0x2F , 0x70 ) ;}
|
||||
if ( ( EPB3 == Masque8 ) && ( DePB3 == 0 ) ) {noteOn(0x80, 0x2F , 0x00 ) ;}
|
||||
|
||||
if ( ( EPB4 == 0 ) && ( DePB4 == Masque16 ) ) { noteOn(0x90, 0x30 , 0x70 ) ;}
|
||||
if ( ( EPB4 == Masque16 ) && ( DePB4 == 0 ) ) { noteOn(0x80, 0x30 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPB5 == 0 ) && ( DePB5 == Masque32 ) ) { noteOn(0x90, 0x31 , 0x70 ) ;}
|
||||
if ( ( EPB5 == Masque32 ) && ( DePB5 == 0 ) ) { noteOn(0x80, 0x31 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPB6 == 0 ) && ( DePB6 == Masque64 ) ) { noteOn(0x90, 0x32 , 0x70 ) ;}
|
||||
if ( ( EPB6 == Masque64 ) && ( DePB6 == 0 ) ) { noteOn(0x80, 0x32 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPB7 == 0 ) && ( DePB7 == Masque128 ) ) { noteOn(0x90, 0x33 , 0x70 ) ;}
|
||||
if ( ( EPB7 == Masque128 ) && ( DePB7 == 0 ) ) { noteOn(0x80, 0x33 , 0x00 ) ;} /* fin de gestion du port B */
|
||||
|
||||
|
||||
|
||||
EPC0 = RegistreC & Masque1 ; /* gestion du port C */
|
||||
EPC1 = RegistreC & Masque2 ;
|
||||
EPC2 = RegistreC & Masque4 ;
|
||||
EPC3 = RegistreC & Masque8 ;
|
||||
EPC4 = RegistreC & Masque16 ;
|
||||
EPC5 = RegistreC & Masque32 ;
|
||||
EPC6 = RegistreC & Masque64 ;
|
||||
EPC7 = RegistreC & Masque128 ;
|
||||
|
||||
if ( ( EPC0 == 0 ) && ( DePC0 == 1 ) ) { noteOn(0x90, 0x34 , 0x70 ) ; } /* gestion du port C */
|
||||
if ( ( EPC0 == 1 ) && ( DePC0 == 0 ) ) { noteOn(0x80, 0x34 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPC1 == 0 ) && ( DePC1 == Masque2 ) ) noteOn(0x90, 0x35 , 0x70 ) ;
|
||||
if ( ( EPC1 == Masque2 ) && ( DePC1 == 0 ) ) noteOn(0x80, 0x35 , 0x00 ) ;
|
||||
|
||||
if ( ( EPC2 == 0 ) && ( DePC2 == Masque4 ) ) { noteOn(0x90, 0x36 , 0x70 ) ;}
|
||||
if ( ( EPC2 == Masque4 ) && ( DePC2 == 0 ) ) { noteOn(0x80, 0x36 , 0x00 ) ; }
|
||||
|
||||
if ( ( EPC3 == 0 ) && ( DePC3 == Masque8 ) ) { noteOn(0x90, 0x37 , 0x70 ) ;}
|
||||
if ( ( EPC3 == Masque8 ) && ( DePC3 == 0 ) ) {noteOn(0x80, 0x37 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPC4 == 0 ) && ( DePC4 == Masque16 ) ) { noteOn(0x90,0x38 , 0x70 ) ;}
|
||||
if ( ( EPC4 == Masque16 ) && ( DePC4 == 0 ) ) { noteOn(0x80, 0x38 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPC5 == 0 ) && ( DePC5 == Masque32 ) ) { noteOn(0x90, 0x39 , 0x70 ) ;}
|
||||
if ( ( EPC5 == Masque32 ) && ( DePC5 == 0 ) ) { noteOn(0x80, 0x39 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPC6 == 0 ) && ( DePC6 == Masque64 ) ) { noteOn(0x90, 0x3A , 0x70 ) ;}
|
||||
if ( ( EPC6 == Masque64 ) && ( DePC6 == 0 ) ) { noteOn(0x80, 0x3A , 0x00 ) ;}
|
||||
|
||||
if ( ( EPC7 == 0 ) && ( DePC7 == Masque128 ) ) { noteOn(0x90, 0x3B , 0x70 ) ;}
|
||||
if ( ( EPC7 == Masque128 ) && ( DePC7 == 0 ) ) { noteOn(0x80, 0x3B , 0x00 ) ;} /* fin de gestion du port C */
|
||||
|
||||
|
||||
|
||||
EPL0 = RegistreL & Masque1 ; /* gestion du port L */
|
||||
EPL1 = RegistreL & Masque2 ;
|
||||
EPL2 = RegistreL & Masque4 ;
|
||||
EPL3 = RegistreL & Masque8 ;
|
||||
EPL4 = RegistreL & Masque16 ;
|
||||
EPL5 = RegistreL & Masque32 ;
|
||||
EPL6 = RegistreL & Masque64 ;
|
||||
EPL7 = RegistreL & Masque128 ;
|
||||
|
||||
if ( ( EPL0 == 0 ) && ( DePL0 == 1 ) ) { noteOn(0x90, 0x3C , 0x70 ) ; } /* gestion du port L */
|
||||
if ( ( EPL0 == 1 ) && ( DePL0 == 0 ) ) { noteOn(0x80, 0x3C , 0x00 ) ;}
|
||||
|
||||
if ( ( EPL1 == 0 ) && ( DePL1 == Masque2 ) ) noteOn(0x90, 0x3D , 0x70 ) ;
|
||||
if ( ( EPL1 == Masque2 ) && ( DePL1 == 0 ) ) noteOn(0x80, 0x3D , 0x00 ) ;
|
||||
|
||||
if ( ( EPL2 == 0 ) && ( DePL2 == Masque4 ) ) { noteOn(0x90, 0x3E , 0x70 ) ;}
|
||||
if ( ( EPL2 == Masque4 ) && ( DePL2 == 0 ) ) { noteOn(0x80, 0x3E , 0x00 ) ; }
|
||||
|
||||
if ( ( EPL3 == 0 ) && ( DePL3 == Masque8 ) ) { noteOn(0x90, 0x3F , 0x70 ) ;}
|
||||
if ( ( EPL3 == Masque8 ) && ( DePL3 == 0 ) ) { noteOn(0x80, 0x3F , 0x00 ) ;}
|
||||
|
||||
if ( ( EPL4 == 0 ) && ( DePL4 == Masque16 ) ) { noteOn(0x90, 0x40 , 0x70 ) ;}
|
||||
if ( ( EPL4 == Masque16 ) && ( DePL4 == 0 ) ) { noteOn(0x80, 0x40 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPL5 == 0 ) && ( DePL5 == Masque32 ) ) { noteOn(0x90, 0x41 , 0x70 ) ;}
|
||||
if ( ( EPL5 == Masque32 ) && ( DePL5 == 0 ) ) { noteOn(0x80, 0x41 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPL6 == 0 ) && ( DePL6 == Masque64 ) ) { noteOn(0x90, 0x42 , 0x70 ) ;}
|
||||
if ( ( EPL6 == Masque64 ) && ( DePL6 == 0 ) ) { noteOn(0x80, 0x42 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPL7 == 0 ) && ( DePL7 == Masque128 ) ) { noteOn(0x90, 0x43 , 0x70 ) ;}
|
||||
if ( ( EPL7 == Masque128 ) && ( DePL7 == 0 ) ) { noteOn(0x80, 0x43 , 0x00 ) ;} /* fin de gestion du port L */
|
||||
|
||||
|
||||
|
||||
|
||||
if ( ( EPA1 == 0 ) && ( DePA1 == Masque2 ) ) noteOn(0x90, 0x26 , 0x70 ) ;
|
||||
if ( ( EPA1 == Masque2 ) && ( DePA1 == 0 ) ) noteOn(0x80, 0x26 , 0x00 ) ;
|
||||
|
||||
|
||||
|
||||
|
||||
if ( ( EPA2 == 0 ) && ( DePA2 == Masque4 ) ) { noteOn(0x90, 0x28 , 0x70 ) ;}
|
||||
if ( ( EPA2 == Masque4 ) && ( DePA2 == 0 ) ) { noteOn(0x80, 0x28 , 0x00 ) ; }
|
||||
|
||||
if ( ( EPA3 == 0 ) && ( DePA3 == Masque8 ) ) { noteOn(0x90, 0x29 , 0x70 ) ;}
|
||||
if ( ( EPA3 == Masque8 ) && ( DePA3 == 0 ) ) {noteOn(0x80, 0x29 , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA4 == 0 ) && ( DePA4 == Masque16 ) ) { noteOn(0x90, 0x2B , 0x70 ) ;}
|
||||
if ( ( EPA4 == Masque16 ) && ( DePA4 == 0 ) ) { noteOn(0x80, 0x2B , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA5 == 0 ) && ( DePA5 == Masque32 ) ) { noteOn(0x90, 0x2D , 0x70 ) ;}
|
||||
if ( ( EPA5 == Masque32 ) && ( DePA5 == 0 ) ) { noteOn(0x80, 0x2D , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA6 == 0 ) && ( DePA6 == Masque64 ) ) { noteOn(0x90, 0x2F , 0x70 ) ;}
|
||||
if ( ( EPA6 == Masque64 ) && ( DePA6 == 0 ) ) { noteOn(0x80, 0x2F , 0x00 ) ;}
|
||||
|
||||
if ( ( EPA7 == 0 ) && ( DePA7 == Masque128 ) ) { noteOn(0x90, 0x30 , 0x70 ) ;}
|
||||
if ( ( EPA7 == Masque128 ) && ( DePA7 == 0 ) ) { noteOn(0x80, 0x30 , 0x00 ) ;}
|
||||
|
||||
|
||||
|
||||
|
||||
DePA0 = EPA0 ;
|
||||
DePA0 = EPA0 ; /* port A */
|
||||
DePA1 = EPA1 ;
|
||||
DePA2 = EPA2 ;
|
||||
DePA3 = EPA3 ;
|
||||
@ -169,6 +404,37 @@ if ( ( EPA0 == 1 ) && ( DePA0 == 0 ) ) { noteOn(0x80, 0x24 , 0x00 ) ;}
|
||||
DePA7 = EPA7 ;
|
||||
|
||||
|
||||
DePB0 = EPB0 ; /* port B */
|
||||
DePB1 = EPB1 ;
|
||||
DePB2 = EPB2 ;
|
||||
DePB3 = EPB3 ;
|
||||
DePB4 = EPB4 ;
|
||||
DePB5 = EPB5 ;
|
||||
DePB6 = EPB6 ;
|
||||
DePB7 = EPB7 ;
|
||||
|
||||
DePC0 = EPC0 ; /* port C */
|
||||
DePC1 = EPC1 ;
|
||||
DePC2 = EPC2 ;
|
||||
DePC3 = EPC3 ;
|
||||
DePC4 = EPC4 ;
|
||||
DePC5 = EPC5 ;
|
||||
DePC6 = EPC6 ;
|
||||
DePC7 = EPC7 ;
|
||||
|
||||
DePL0 = EPL0 ; /* port L */
|
||||
DePL1 = EPL1 ;
|
||||
DePL2 = EPL2 ;
|
||||
DePL3 = EPL3 ;
|
||||
DePL4 = EPL4 ;
|
||||
DePL5 = EPL5 ;
|
||||
DePL6 = EPL6 ;
|
||||
DePL7 = EPL7 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user